The present disclosure relates to a semiconductor memory device, and more particularly, to a write driving circuit.
FIG. 1 illustrates a block diagram of a conventional write driving circuit.
Referring to FIG. 1, the conventional write driving circuit includes an input buffer 100, an input latch 200, a serial-to-parallel converter 300, and a global input/output (GIO) write driver 400. The write driving circuit applied to an X16 DDR2 memory semiconductor is illustrated in FIG. 1.
The input buffer 100 (101-116) converts data signals DIN<0:15> input through data input pads into complementary metal-oxide semiconductor (CMOS) level signals. A signal WTEN enables the input buffer 100 in a write operation.
The input latch 200 (201-216) latches output signals of the input buffers 100 (101-116) according to a strobe signal (not shown).
The serial-to-parallel converter 300 (301-316) converts serial data signals having passed the input buffers 100 (101-116) and the input latches 200 (201-216) into parallel data signals. Bit data signals input on a 1-bit basis are converted into 4-bit data signals by the serial-to-parallel converter 300 (301-316).
The GIO write driver 400 drives GIO lines according to the input four-bit data signals.
FIG. 2 illustrates a circuit diagram for the write driver of FIG. 1. Referring to FIG. 2, a conventional write driver 400 receives four-bit data signals DINEV0, DINOD0, DINEV1 and DINOD1 output from the serial-to-parallel converter 300 to output signals GIOQ0, GIOQ1, GIOQ2 and GIOQ3.
When the signal DINEV0 has a logic high level, both inverters IV1 and IV2 output low level signals to turn on a PMOS transistor P1 and turn off a NMOS transistor N1, thereby outputting a signal GIOQ0 of a logic high level. When the signal DINEV0 has a logic low level, both the inverters IV1 and IV2 output high level signals to turn off the PMOS transistor P1 and turn on the NMOS transistor N1, thereby outputting a signal GIOQ0 of a logic low level.
The operations of inverters IV3 to IV8, PMOS transistors P2 to P4 and NMOS transistors N2 to N4 according to the signals DINOD0, DINEV1 and DINOD1 are the same as the operations of the inverters IV1 and IV2, the PMOS transistor P1 and the NMOS transistor N1 according to the signal DINEV0.
A burn-in test for a semiconductor memory is a lifetime test which is performed on a lot of chips for a long time under worst case conditions. It is generally desirable to perform a burn-in test on a lot of chips at a time so as to improve test productivity. However, in semiconductor chips using all of the sixteen data input pins, there is a limitation in testing a lot of chips using sixteen data pins at a time because a test apparatus typically has finite input and output terminals.